//======  EVB Setting =========//
JDEVB_IF(DSI_VDO);
JDEVB_DSIPixelFormate(18bpp);//16bpp,18bpp-L,24bpp
JDEVB_RSOX(360);
JDEVB_RSOY(360);
JDEVB_VS(1);
JDEVB_VBP(4);
JDEVB_VFP(7);
JDEVB_HS(20);
JDEVB_HBP(22);
JDEVB_HFP(20);
JDEVB_DSILANE(1);	//DSI Lane
JDEVB_DOTCLK(9.42); //60 Hz

JDEVB_SSDIO(1.80);  //SSD_IOVCC Power     
JDEVB_IOVCC(3.3);  //Connect to FPC IOVCC  	
JDEVB_VCI(3.3);   //Connect to FPC VCC

Delayms(10);
//======  initial setting =========//

{
Solomon_REG_WR(0x00B7,0x0150);
Sleep(1);
Solomon_REG_WR(0x00D6,0x0005);
Sleep(1);
Solomon_REG_WR(0x00B9,0xC000);
Sleep(1);
Solomon_REG_WR(0x00BA,0x420F);
Sleep(1);
Solomon_REG_WR(0x00CF,0x0000);
Sleep(1);
Solomon_REG_WR(0x00D0,0x0010);
Sleep(1);
Solomon_REG_WR(0x00DE,0x0000);
Sleep(1);
Solomon_REG_WR(0x00BB,0x0002);
Sleep(1);
Solomon_REG_WR(0x00B9,0xC001);
Sleep(1);
Solomon_REG_WR(0x00C9,0x0501);
Sleep(1);
Solomon_REG_WR(0x00CA,0x0A01);
Sleep(1);
Solomon_REG_WR(0x00CB,0x0210);
Sleep(1);
Solomon_REG_WR(0x00CC,0x0304);
Sleep(1);
Solomon_REG_WR(0x00B8,0x0000);
Sleep(1);
Solomon_REG_WR(0x00BD,0x0000);
Sleep(1);
}

SSD_Start();

//Page 0
SSD_Number(0x02);
SSD_CMD(0xDE);
SSD_PAR(0x00);

//SET_PASSWD 
SSD_Number(0x03);
SSD_CMD(0xDF);
SSD_PAR(0x98);
SSD_PAR(0x55);

//VGPOW_SET
SSD_Number(0x02);
SSD_CMD(0xB2);
SSD_PAR(0x1F);//FMA=6%

//GAMMA_SET
SSD_Number(0x05);
SSD_CMD(0xB7);
SSD_PAR(0x01);
SSD_PAR(0x2D);
SSD_PAR(0x01);
SSD_PAR(0x55);

//DCDC_SEL
SSD_Number(0x07);
SSD_CMD(0xBB);
SSD_PAR(0x1B);
SSD_PAR(0x64);
SSD_PAR(0xC4);
SSD_PAR(0x0E);  //VGH=12V, VGL=-11.5V
SSD_PAR(0x3E);
SSD_PAR(0xF5);

//DCDC_SEL2
SSD_Number(0x05);
SSD_CMD(0xBC);
SSD_PAR(0x03);
SSD_PAR(0x20);
SSD_PAR(0xF3);
SSD_PAR(0xC0);

//SETSTBA
SSD_Number(0x03);
SSD_CMD(0xC0);
SSD_PAR(0x22);
SSD_PAR(0xA1);

//SETRGBCYC
SSD_Number(0x0C);
SSD_CMD(0xC3);
SSD_PAR(0x00);  // -, RGB_INV_P[1:0], RGB_INV_I[1:0], IDLE_TYPE, RGB_INV_NP[1:0]
SSD_PAR(0x02);  // -, -, -, -, RGB_GND[3:0]
SSD_PAR(0x2A);  // RGB_NEQ1[3:0], RGB_PEQ1[3:0]
SSD_PAR(0x0B);  // -, -, -, RGB_PEQ2[4:0]
SSD_PAR(0x08);  // -, -, -, RGB_NEQ2[4:0]
SSD_PAR(0x48);  // RGB_CHGEN_OFF[1:0], RGB_CHGEN_ON[5:0]
SSD_PAR(0x08);  // GAOPOFF_1ST_OFF, GAOPOFF_POL, RGB_OFF[5:0]
SSD_PAR(0x04);
SSD_PAR(0x62);
SSD_PAR(0x30);
SSD_PAR(0x30);

//SET_TCON
SSD_Number(0x0C);
SSD_CMD(0xC4);
SSD_PAR(0x40);  // -, LN[8], SLT_NP[8], SLT_I[8], VBFP_RATIO[1:0], TE_OPT[1:0]
SSD_PAR(0x00);  // -, TE_DELAY[6:0]
SSD_PAR(0xAD);  // DUAL_EN, -, VAR_RESO_X[5:0]
SSD_PAR(0x68);  // LN[7:0]
SSD_PAR(0x43);  // SLT_NP[7:0]
SSD_PAR(0x07);  // VFP_NP[7:0]
SSD_PAR(0x04);  // VFP_NP[8], VBP_NP[6:0]
SSD_PAR(0x16);  // -, HBP_NP[6:0]
SSD_PAR(0x43);  // SLT_I[7:0]
SSD_PAR(0x07);  // VFP_I[7:0]
SSD_PAR(0x04);  // VFP_I[8], VBP_I[6:0]

//SET_R_GAMMA_Fit_G2.2_0108
SSD_Number(0x21);
SSD_CMD(0xC8); //G2.5
SSD_PAR(0x3F); //0x3F
SSD_PAR(0x31); //0x30
SSD_PAR(0x28); //0x26
SSD_PAR(0x25); //0x23
SSD_PAR(0x25); //0x23
SSD_PAR(0x27); //0x24
SSD_PAR(0x22); //0x1E
SSD_PAR(0x22); //0x1E
SSD_PAR(0x20); //0x1D
SSD_PAR(0x1F); //0x1C
SSD_PAR(0x1C); //0x18
SSD_PAR(0x12); //0x0C
SSD_PAR(0x0F); //0x09
SSD_PAR(0x0B); //0x05
SSD_PAR(0x02); //0x01
SSD_PAR(0x02); //0x02
SSD_PAR(0x3F); //0x3F
SSD_PAR(0x31); //0x30
SSD_PAR(0x28); //0x27
SSD_PAR(0x25); //0x23
SSD_PAR(0x25); //0x23
SSD_PAR(0x27); //0x24
SSD_PAR(0x22); //0x1F
SSD_PAR(0x22); //0x1E
SSD_PAR(0x20); //0x1C
SSD_PAR(0x1F); //0x1C
SSD_PAR(0x1C); //0x18
SSD_PAR(0x12); //0x0C
SSD_PAR(0x0F); //0x09
SSD_PAR(0x0B); //0x05
SSD_PAR(0x02); //0x01
SSD_PAR(0x02); //0x02

//LE_CTRL
SSD_Number(0x03);
SSD_CMD(0xD3);
SSD_PAR(0x28);
SSD_PAR(0x13);

//RAMCTRL
SSD_Number(0x03);
SSD_CMD(0xD7);
SSD_PAR(0x18);
SSD_PAR(0x30);

//OTP_PROG
SSD_Number(0x07);
SSD_CMD(0xD9);
SSD_PAR(0x00);
SSD_PAR(0x00);
SSD_PAR(0xFF);
SSD_PAR(0x00);
SSD_PAR(0xF0);	//OTP_PRO_TIMES
SSD_PAR(0x00);

//Page 1
SSD_Number(0x02);
SSD_CMD(0xDE);
SSD_PAR(0x01);

//DCDC_OPT
SSD_Number(0x09);
SSD_CMD(0xB7);
SSD_PAR(0x13);
SSD_PAR(0xE7);
SSD_PAR(0x64);
SSD_PAR(0x39);
SSD_PAR(0x06);
SSD_PAR(0x36);
SSD_PAR(0x19);
SSD_PAR(0x1C);

//GAMMA_POWER_TEST
SSD_Number(0x02);
SSD_CMD(0xBE);
SSD_PAR(0x00);

//SETRGBCYC2
SSD_Number(0x04);
SSD_CMD(0xC1);
SSD_PAR(0x00);
SSD_PAR(0x4A);
SSD_PAR(0x80);

//SETSTBA2
SSD_Number(0x05);
SSD_CMD(0xC2);
SSD_PAR(0x00);
SSD_PAR(0x16);
SSD_PAR(0xDA);
SSD_PAR(0xE7);

//SET_GIP_ON_OFF
SSD_Number(0x09);
SSD_CMD(0xC7);
SSD_PAR(0x00);
SSD_PAR(0x00);
SSD_PAR(0x00);  // STV_ON[7:0]
SSD_PAR(0x38);  // STV_OFF[7:0]
SSD_PAR(0x08);  // ETV_ON[7:0]
SSD_PAR(0x08);  // ETV_OFF[7:0]
SSD_PAR(0x00);  // VEN_ON[7:0]
SSD_PAR(0x01);  // VEN_OFF[7:0]

//SET_GIP_ON_OFF_2
SSD_Number(0x07);
SSD_CMD(0xC8);
SSD_PAR(0x00);
SSD_PAR(0x00);
SSD_PAR(0x00);
SSD_PAR(0x00);
SSD_PAR(0x15);  // CKV0_ON[7:0]
SSD_PAR(0x3B);  // Count up CKV0_OFF=0x3B

//SET_GIP_L
SSD_Number(0x06);
SSD_CMD(0xC9);
SSD_PAR(0x00);  // CGOUT0_L=STV0
SSD_PAR(0x16);  // CGOUT1_L=INV(VEN1)
SSD_PAR(0x06);  // CGOUT2_L=CKV2
SSD_PAR(0x04);  // CGOUT3_L=CKV0
SSD_PAR(0x0A);  // CGOUT4_L=CKV6

//SET_GIP_L_2
SSD_Number(0x06);
SSD_CMD(0xCA);
SSD_PAR(0x08);  // CGOUT5_L=CKV4
SSD_PAR(0x35);  // CGOUT6_L=INV(VEN0)
SSD_PAR(0x16);  // CGOUT7_L=INV(VEN1)
SSD_PAR(0x1F);  // CGOUT8_L=VGL
SSD_PAR(0x1F);  // CGOUT9_L=VGL

//SET_GIP_R
SSD_Number(0x06);
SSD_CMD(0xCB);
SSD_PAR(0x01);  // CGOUT0_R=STV1
SSD_PAR(0x16);  // CGOUT1_R=INV(VEN1)
SSD_PAR(0x07);  // CGOUT2_R=CKV3
SSD_PAR(0x05);  // CGOUT3_R=CKV1
SSD_PAR(0x0B);  // CGOUT4_R=CKV7

//SET_GIP_R_2
SSD_Number(0x06);
SSD_CMD(0xCC);
SSD_PAR(0x09);  // CGOUT5_R=CKV5
SSD_PAR(0x35);  // CGOUT6_R=INV(VEN0)
SSD_PAR(0x16);  // CGOUT7_R=INV(VEN1)
SSD_PAR(0x1F);  // CGOUT8_R=VGL
SSD_PAR(0x1F);  // CGOUT9_R=VGL

//SET_GIP_L_GS
SSD_Number(0x06);
SSD_CMD(0xCD);
SSD_PAR(0x01);  // CGOUT0_L_GS=STV1
SSD_PAR(0x16);  // CGOUT1_L_GS=INV(VEN1)
SSD_PAR(0x09);  // CGOUT2_L_GS=CKV5
SSD_PAR(0x0B);  // CGOUT3_L_GS=CKV7
SSD_PAR(0x05);  // CGOUT4_L_GS=CKV1

//SET_GIP_L_GS_2
SSD_Number(0x06);
SSD_CMD(0xCE);
SSD_PAR(0x07);  // CGOUT5_L_GS=CKV3
SSD_PAR(0x15);  // CGOUT6_L_GS=INV(VEN0)
SSD_PAR(0x1F);  // CGOUT7_L_GS=VGL
SSD_PAR(0x16);  // CGOUT8_L_GS=INV(VEN1)
SSD_PAR(0x1F);  // CGOUT9_L_GS=VGL

//SET_GIP_R_GS
SSD_Number(0x06);
SSD_CMD(0xCF);
SSD_PAR(0x00);  // CGOUT0_R_GS=STV0
SSD_PAR(0x16);  // CGOUT1_R_GS=INV(VEN1)
SSD_PAR(0x08);  // CGOUT2_R_GS=CKV4
SSD_PAR(0x0A);  // CGOUT3_R_GS=CKV6
SSD_PAR(0x04);  // CGOUT4_R_GS=CKV0

//SET_GIP_R_GS_2
SSD_Number(0x06);
SSD_CMD(0xD0);
SSD_PAR(0x06);  // CGOUT5_R_GS=CKV2
SSD_PAR(0x15);  // CGOUT6_R_GS=INV(VEN0)
SSD_PAR(0x1F);  // CGOUT7_R_GS=VGL
SSD_PAR(0x16);  // CGOUT8_R_GS=INV(VEN1)
SSD_PAR(0x1F);  // CGOUT9_R_GS=VGL

//SETGIP1
SSD_Number(0x03);
SSD_CMD(0xD1);
SSD_PAR(0x02);  // -, -, STV_S0[5:0]
SSD_PAR(0x30);  // STV_W0[3:0], -, -, -

//SETGIP2
SSD_Number(0x06);
SSD_CMD(0xD2);
SSD_PAR(0x02);
SSD_PAR(0x03);
SSD_PAR(0x52);
SSD_PAR(0xDF);
SSD_PAR(0xDD);

//SETGIP3
SSD_Number(0x04);
SSD_CMD(0xD3);
SSD_PAR(0x3B);  // CKV0_CON, -, CKV0_NUM[2:0], CKV0_W[2:0]
SSD_PAR(0x04);  // FRAME_CNT_INVERSE, GIP_FRAME_CNT_OPT, CKV0_S0[5:0]
SSD_PAR(0x48);  // CKV_SW_OPT, SW_OPTION, CKV0_DUM[5:0]

//SETGIP5
SSD_Number(0x08);
SSD_CMD(0xD5);
SSD_PAR(0x10);  // -, -, -, GCK_EQ_VGHPRE[4:0]
SSD_PAR(0x10);  // -, -, -, GEQ_VGHPRE[4:0]
SSD_PAR(0x07);  // -, -, -, GEQ_VCI_GND1[4:0]
SSD_PAR(0x07);  // -, -, -, GEQ_VCI_GND2[4:0]
SSD_PAR(0x0F);  // -, -, -, -, VGHPRE_EQ_2X[3:0]
SSD_PAR(0x94);  // GIP_GAS_LVL[2:0], GIP_GAS_DLY[4:0]
SSD_PAR(0x26);  // -, -, GIP_RST_EN, GIP_GAS_EQ[4:0]

//SET_GIP_OPT
SSD_Number(0x04);
SSD_CMD(0xD6);
SSD_PAR(0x00); 
SSD_PAR(0x00); 
SSD_PAR(0x40); 

//SETGIP_PRD
SSD_Number(0x04);
SSD_CMD(0xD7);
SSD_PAR(0x00);  // -, -, -, -, INIT_PORCH[3:0]
SSD_PAR(0x00);  // GIP_GAS_EN, ESD_SLPIN_TEST[1:0], END_W[2:0], INIT_LINE_OPT, END_LINE_OPT
SSD_PAR(0x20);  // -, GIP_HIZ, GIP_SEL_EQ, -, -, -, -, -

//Page 2
SSD_Number(0x02);
SSD_CMD(0xDE);
SSD_PAR(0x02);

//GRAM_PWR_SET
SSD_Number(0x02);
SSD_CMD(0xB6);
SSD_PAR(0x1C);

//Page 0
SSD_Number(0x02);
SSD_CMD(0xDE);
SSD_PAR(0x00);

//Memory Clear Set R
SSD_Number(0x02);
SSD_CMD(0x4D);
SSD_PAR(0x00);

//Memory Clear Set G
SSD_Number(0x02);
SSD_CMD(0x4E);
SSD_PAR(0x00);

//Memory Clear Set B
SSD_Number(0x02);
SSD_CMD(0x4F);
SSD_PAR(0x00);

//Memory Clear Act
SSD_Number(0x02);
SSD_CMD(0x4C);
SSD_PAR(0x01);
Delayms(10);

//Memory Clear Act
SSD_Number(0x02);
SSD_CMD(0x4C);
SSD_PAR(0x00);

//Column Address Set
SSD_Number(0x05);
SSD_CMD(0x2A);
SSD_PAR(0x00);
SSD_PAR(0x00);
SSD_PAR(0x01);
SSD_PAR(0x68);

//Row Address Set
SSD_Number(0x05);
SSD_CMD(0x2B);
SSD_PAR(0x00);
SSD_PAR(0x00);
SSD_PAR(0x01);
SSD_PAR(0x68);

SSD_Number(0x01);
SSD_CMD(0x35);

//Interface Pixel Format
SSD_Number(0x02);
SSD_CMD(0x3A);
SSD_PAR(0x66);

SSD_Number(0x01);
SSD_CMD(0x11);
Delayms(120);


SSD_Number(0x01);
SSD_CMD(0x29);
Delayms(20);

SSD_Stop();
{
Solomon_REG_WR(0x00B7,0x0151);
Sleep(1);
Solomon_REG_WR(0x00B1,0x0114);
Sleep(1);
Solomon_REG_WR(0x00B2,0x052A);
Sleep(1);
Solomon_REG_WR(0x00B3,0x0714);
Sleep(1);
Solomon_REG_WR(0x00B4,0x0168);
Sleep(1);
Solomon_REG_WR(0x00B5,0x0168);
Sleep(1);
Solomon_REG_WR(0x00B6,0x0099);
Sleep(1);
Solomon_REG_WR(0x00B7,0x0159);
Sleep(10);
}